Back to home page

EIC code displayed by LXR

 
 

    


File indexing completed on 2025-01-30 09:33:56

0001 /*
0002  * Distributed under the Boost Software License, Version 1.0.
0003  * (See accompanying file LICENSE_1_0.txt or copy at
0004  * http://www.boost.org/LICENSE_1_0.txt)
0005  *
0006  * Copyright (c) 2020 Andrey Semashev
0007  */
0008 /*!
0009  * \file   atomic/detail/fence_arch_ops_gcc_alpha.hpp
0010  *
0011  * This header contains implementation of the \c fence_arch_operations struct.
0012  */
0013 
0014 #ifndef BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ALPHA_HPP_INCLUDED_
0015 #define BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ALPHA_HPP_INCLUDED_
0016 
0017 #include <boost/memory_order.hpp>
0018 #include <boost/atomic/detail/config.hpp>
0019 #include <boost/atomic/detail/header.hpp>
0020 
0021 #ifdef BOOST_HAS_PRAGMA_ONCE
0022 #pragma once
0023 #endif
0024 
0025 namespace boost {
0026 namespace atomics {
0027 namespace detail {
0028 
0029 //! Fence operations for Alpha
0030 struct fence_arch_operations_gcc_alpha
0031 {
0032     static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
0033     {
0034         if (order != memory_order_relaxed)
0035             __asm__ __volatile__ ("mb" ::: "memory");
0036     }
0037 
0038     static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
0039     {
0040         if (order != memory_order_relaxed)
0041             __asm__ __volatile__ ("" ::: "memory");
0042     }
0043 };
0044 
0045 typedef fence_arch_operations_gcc_alpha fence_arch_operations;
0046 
0047 } // namespace detail
0048 } // namespace atomics
0049 } // namespace boost
0050 
0051 #include <boost/atomic/detail/footer.hpp>
0052 
0053 #endif // BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ALPHA_HPP_INCLUDED_