include/QtCore/qsimd.h

0001 // Copyright (C) 2020 The Qt Company Ltd.
0002 // Copyright (C) 2022 Intel Corporation.
0003 // SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
0004
0005 #ifndef QSIMD_H
0006 #define QSIMD_H
0007
0008 #include <QtCore/qglobal.h>
0009
0010 /*
0011  * qconfig.h defines the QT_COMPILER_SUPPORTS_XXX macros.
0012  * They mean the compiler supports the necessary flags and the headers
0013  * for the x86 and ARM intrinsics.
0014  *
0015  * Supported instruction set extensions are:
0016  *   Flag      | Arch
0017  *  neon       | ARM
0018  *  sve        | ARM
0019  *  mips_dsp   | mips
0020  *  mips_dspr2 | mips
0021  *  sse2       | x86
0022  *  sse4_1     | x86
0023  *  sse4_2     | x86
0024  *  avx        | x86
0025  *  avx2       | x86
0026  *  lsx        | loongarch
0027  *  lasx       | loongarch
0028  *
0029  * Code can use the following constructs to determine compiler support & status:
0030  * - #if QT_COMPILER_USES(XXX) (e.g: #if QT_COMPILER_USES(neon) or QT_COMPILER_USES(sse4_1)
0031  *   If this test passes, then the compiler is already generating code using the
0032  *   given instruction set. The intrinsics for those instructions are
0033  *   #included and can be used without restriction or runtime check.
0034  *
0035  * Code that requires runtime detection and different code paths at runtime is
0036  * currently not supported here, have a look at qsimd_p.h for support.
0037  */
0038
0039 #define QT_COMPILER_USES(feature) (1/QT_COMPILER_USES_##feature == 1)
0040
0041 #if defined(Q_PROCESSOR_ARM) && defined(__ARM_NEON) || defined(__ARM_NEON__) || defined(_M_ARM64)
0042 #  include <arm_neon.h>
0043 #  define QT_COMPILER_USES_neon 1
0044 #else
0045 #  define QT_COMPILER_USES_neon -1
0046 #endif
0047
0048 // To avoid to many untestable fringe cases we so far only support 64bit LE in SVE code
0049 // The test for QT_COMPILER_SUPPORTS_SVE ensures the intrinsics exists
0050 #if defined(Q_PROCESSOR_ARM_64) && defined(__ARM_FEATURE_SVE) && defined(Q_LITTLE_ENDIAN) && defined(QT_COMPILER_SUPPORTS_SVE)
0051 #  include <arm_sve.h>
0052 #  define QT_COMPILER_USES_sve 1
0053 #else
0054 #  define QT_COMPILER_USES_sve -1
0055 #endif
0056
0057 #if defined(Q_PROCESSOR_MIPS) && (defined(__MIPS_DSP__) || (defined(__mips_dsp) && defined(Q_PROCESSOR_MIPS_32)))
0058 #  define QT_COMPILER_USES_mips_dsp 1
0059 #else
0060 #  define QT_COMPILER_USES_mips_dsp -1
0061 #endif
0062
0063 #if defined(Q_PROCESSOR_MIPS) && (defined(__MIPS_DSPR2__) || (defined(__mips_dspr2) && defined(Q_PROCESSOR_MIPS_32)))
0064 #  define QT_COMPILER_USES_mips_dspr2 1
0065 #else
0066 #  define QT_COMPILER_USES_mips_dspr2 -1
0067 #endif
0068
0069 #if defined(Q_PROCESSOR_LOONGARCH) && defined(__loongarch_sx)
0070 #  include <lsxintrin.h>
0071 #  define QT_COMPILER_USES_lsx 1
0072 #else
0073 #  define QT_COMPILER_USES_lsx -1
0074 #endif
0075
0076 #if defined(Q_PROCESSOR_LOONGARCH) && defined(__loongarch_asx)
0077 #  include <lasxintrin.h>
0078 #  define QT_COMPILER_USES_lasx 1
0079 #else
0080 #  define QT_COMPILER_USES_lasx -1
0081 #endif
0082
0083 #if defined(Q_PROCESSOR_X86) && defined(Q_CC_MSVC)
0084 // MSVC doesn't define __SSE2__, so do it ourselves
0085 #  if (defined(_M_X64) || _M_IX86_FP >= 2) && defined(QT_COMPILER_SUPPORTS_SSE2)
0086 #    define __SSE__ 1
0087 #    define __SSE2__ 1
0088 #  endif
0089 #  if (defined(_M_AVX) || defined(__AVX__))
0090 // Visual Studio defines __AVX__ when /arch:AVX is passed, but not the earlier macros
0091 // See: https://msdn.microsoft.com/en-us/library/b0084kay.aspx
0092 #    define __SSE3__                        1
0093 #    define __SSSE3__                       1
0094 #    define __SSE4_1__                      1
0095 #    define __SSE4_2__                      1
0096 #    define __POPCNT__                      1
0097 #    ifndef __AVX__
0098 #      define __AVX__                       1
0099 #    endif
0100 #  endif
0101 #  ifdef __SSE2__
0102 #    define QT_VECTORCALL __vectorcall
0103 #  endif
0104 #  ifdef __AVX2__
0105 // MSVC defines __AVX2__ with /arch:AVX2
0106 #    define __F16C__                        1
0107 #    define __RDRND__                       1
0108 #    define __FMA__                         1
0109 #    define __BMI__                         1
0110 #    define __BMI2__                        1
0111 #    define __MOVBE__                       1
0112 #    define __LZCNT__                       1
0113 #  endif
0114 // Starting with /arch:AVX512, MSVC defines all the macros
0115 #endif
0116
0117 #if defined(Q_PROCESSOR_X86) && defined(__SSE2__)
0118 #  include <immintrin.h>
0119 #  define QT_COMPILER_USES_sse2 1
0120 #else
0121 #  define QT_COMPILER_USES_sse2 -1
0122 #endif
0123
0124 #if defined(Q_PROCESSOR_X86) && defined(__SSE3__)
0125 #  define QT_COMPILER_USES_sse3 1
0126 #else
0127 #  define QT_COMPILER_USES_sse3 -1
0128 #endif
0129
0130 #if defined(Q_PROCESSOR_X86) && defined(__SSSE3__)
0131 #  define QT_COMPILER_USES_ssse3 1
0132 #else
0133 #  define QT_COMPILER_USES_ssse3 -1
0134 #endif
0135
0136 #if defined(Q_PROCESSOR_X86) && defined(__SSE4_1__)
0137 #  define QT_COMPILER_USES_sse4_1 1
0138 #else
0139 #  define QT_COMPILER_USES_sse4_1 -1
0140 #endif
0141
0142 #if defined(Q_PROCESSOR_X86) && defined(__SSE4_2__)
0143 #  define QT_COMPILER_USES_sse4_2 1
0144 #else
0145 #  define QT_COMPILER_USES_sse4_2 -1
0146 #endif
0147
0148 #if defined(Q_PROCESSOR_X86) && defined(__AVX__)
0149 #  define QT_COMPILER_USES_avx 1
0150 #else
0151 #  define QT_COMPILER_USES_avx -1
0152 #endif
0153
0154 #if defined(Q_PROCESSOR_X86) && defined(__AVX2__)
0155 #  define QT_COMPILER_USES_avx2 1
0156 #else
0157 #  define QT_COMPILER_USES_avx2 -1
0158 #endif
0159
0160 #ifndef QT_VECTORCALL
0161 #define QT_VECTORCALL
0162 #endif
0163
0164 QT_BEGIN_NAMESPACE
0165 QT_END_NAMESPACE
0166
0167 #endif // QSIMD_H