include/QtCore/qsimd.h

0001 // Copyright (C) 2020 The Qt Company Ltd.
0002 // Copyright (C) 2022 Intel Corporation.
0003 // SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
0004 // Qt-Security score:significant reason:default
0005
0006 #ifndef QSIMD_H
0007 #define QSIMD_H
0008
0009 #include <QtCore/qglobal.h>
0010
0011 /*
0012  * qconfig.h defines the QT_COMPILER_SUPPORTS_XXX macros.
0013  * They mean the compiler supports the necessary flags and the headers
0014  * for the x86 and ARM intrinsics.
0015  *
0016  * Supported instruction set extensions are:
0017  *   Flag      | Arch
0018  *  neon       | ARM
0019  *  sve        | ARM
0020  *  mips_dsp   | mips
0021  *  mips_dspr2 | mips
0022  *  sse2       | x86
0023  *  sse4_1     | x86
0024  *  sse4_2     | x86
0025  *  avx        | x86
0026  *  avx2       | x86
0027  *  lsx        | loongarch
0028  *  lasx       | loongarch
0029  *
0030  * Code can use the following constructs to determine compiler support & status:
0031  * - #if QT_COMPILER_USES(XXX) (e.g: #if QT_COMPILER_USES(neon) or QT_COMPILER_USES(sse4_1)
0032  *   If this test passes, then the compiler is already generating code using the
0033  *   given instruction set. The intrinsics for those instructions are
0034  *   #included and can be used without restriction or runtime check.
0035  *
0036  * Code that requires runtime detection and different code paths at runtime is
0037  * currently not supported here, have a look at qsimd_p.h for support.
0038  */
0039
0040 #define QT_COMPILER_USES(feature) (1/QT_COMPILER_USES_##feature == 1)
0041
0042 #if defined(Q_PROCESSOR_ARM) && defined(__ARM_NEON) || defined(__ARM_NEON__) || defined(_M_ARM64)
0043 #  include <arm_neon.h>
0044 #  define QT_COMPILER_USES_neon 1
0045 #else
0046 #  define QT_COMPILER_USES_neon -1
0047 #endif
0048
0049 // To avoid to many untestable fringe cases we so far only support 64bit LE in SVE code
0050 // The test for QT_COMPILER_SUPPORTS_SVE ensures the intrinsics exists
0051 #if defined(Q_PROCESSOR_ARM_64) && defined(__ARM_FEATURE_SVE) && defined(Q_LITTLE_ENDIAN) && defined(QT_COMPILER_SUPPORTS_SVE)
0052 #  include <arm_sve.h>
0053 #  define QT_COMPILER_USES_sve 1
0054 #else
0055 #  define QT_COMPILER_USES_sve -1
0056 #endif
0057
0058 #if defined(Q_PROCESSOR_MIPS) && (defined(__MIPS_DSP__) || (defined(__mips_dsp) && defined(Q_PROCESSOR_MIPS_32)))
0059 #  define QT_COMPILER_USES_mips_dsp 1
0060 #else
0061 #  define QT_COMPILER_USES_mips_dsp -1
0062 #endif
0063
0064 #if defined(Q_PROCESSOR_MIPS) && (defined(__MIPS_DSPR2__) || (defined(__mips_dspr2) && defined(Q_PROCESSOR_MIPS_32)))
0065 #  define QT_COMPILER_USES_mips_dspr2 1
0066 #else
0067 #  define QT_COMPILER_USES_mips_dspr2 -1
0068 #endif
0069
0070 #if defined(Q_PROCESSOR_LOONGARCH) && defined(__loongarch_sx)
0071 #  include <lsxintrin.h>
0072 #  define QT_COMPILER_USES_lsx 1
0073 #else
0074 #  define QT_COMPILER_USES_lsx -1
0075 #endif
0076
0077 #if defined(Q_PROCESSOR_LOONGARCH) && defined(__loongarch_asx)
0078 #  include <lasxintrin.h>
0079 #  define QT_COMPILER_USES_lasx 1
0080 #else
0081 #  define QT_COMPILER_USES_lasx -1
0082 #endif
0083
0084 #if defined(Q_PROCESSOR_X86) && defined(Q_CC_MSVC)
0085 // MSVC doesn't define __SSE2__, so do it ourselves
0086 #  if (defined(_M_X64) || _M_IX86_FP >= 2) && defined(QT_COMPILER_SUPPORTS_SSE2)
0087 #    define __SSE__ 1
0088 #    define __SSE2__ 1
0089 #  endif
0090 #  if (defined(_M_AVX) || defined(__AVX__))
0091 // Visual Studio defines __AVX__ when /arch:AVX is passed, but not the earlier macros
0092 // See: https://msdn.microsoft.com/en-us/library/b0084kay.aspx
0093 #    define __SSE3__                        1
0094 #    define __SSSE3__                       1
0095 #    define __SSE4_1__                      1
0096 #    define __SSE4_2__                      1
0097 #    define __POPCNT__                      1
0098 #    ifndef __AVX__
0099 #      define __AVX__                       1
0100 #    endif
0101 #  endif
0102 #  ifdef __SSE2__
0103 #    define QT_VECTORCALL __vectorcall
0104 #  endif
0105 #  ifdef __AVX2__
0106 // MSVC defines __AVX2__ with /arch:AVX2
0107 #    define __F16C__                        1
0108 #    define __RDRND__                       1
0109 #    define __FMA__                         1
0110 #    define __BMI__                         1
0111 #    define __BMI2__                        1
0112 #    define __MOVBE__                       1
0113 #    define __LZCNT__                       1
0114 #  endif
0115 // Starting with /arch:AVX512, MSVC defines all the macros
0116 #endif
0117
0118 #if defined(Q_PROCESSOR_X86) && defined(__SSE2__)
0119 #  include <immintrin.h>
0120 #  define QT_COMPILER_USES_sse2 1
0121 #else
0122 #  define QT_COMPILER_USES_sse2 -1
0123 #endif
0124
0125 #if defined(Q_PROCESSOR_X86) && defined(__SSE3__)
0126 #  define QT_COMPILER_USES_sse3 1
0127 #else
0128 #  define QT_COMPILER_USES_sse3 -1
0129 #endif
0130
0131 #if defined(Q_PROCESSOR_X86) && defined(__SSSE3__)
0132 #  define QT_COMPILER_USES_ssse3 1
0133 #else
0134 #  define QT_COMPILER_USES_ssse3 -1
0135 #endif
0136
0137 #if defined(Q_PROCESSOR_X86) && defined(__SSE4_1__)
0138 #  define QT_COMPILER_USES_sse4_1 1
0139 #else
0140 #  define QT_COMPILER_USES_sse4_1 -1
0141 #endif
0142
0143 #if defined(Q_PROCESSOR_X86) && defined(__SSE4_2__)
0144 #  define QT_COMPILER_USES_sse4_2 1
0145 #else
0146 #  define QT_COMPILER_USES_sse4_2 -1
0147 #endif
0148
0149 #if defined(Q_PROCESSOR_X86) && defined(__AVX__)
0150 #  define QT_COMPILER_USES_avx 1
0151 #else
0152 #  define QT_COMPILER_USES_avx -1
0153 #endif
0154
0155 #if defined(Q_PROCESSOR_X86) && defined(__AVX2__)
0156 #  define QT_COMPILER_USES_avx2 1
0157 #else
0158 #  define QT_COMPILER_USES_avx2 -1
0159 #endif
0160
0161 #ifndef QT_VECTORCALL
0162 #define QT_VECTORCALL
0163 #endif
0164
0165 QT_BEGIN_NAMESPACE
0166 QT_END_NAMESPACE
0167
0168 #endif // QSIMD_H